Design Environment Challenges: Using PLM for Semiconductors
Following up on an earlier blog post where we discussed what is product lifecycle management for semiconductors, in this blog we will delve deeper into the challenges that PLM presents for a semiconductor design environment.
Although PLM tools have seen some success in industries such as defense, automobile, aerospace, and others with large design teams and well-established methodologies, the adoption rate in the semiconductor space has been slow.
PLM in Semiconductor Design Environments – Adoption Challenges
There are a number of challenges that lead to a lower adoption of PLM in semiconductor design, including the following:
PLM Solutions Work Best in a Static Design Environment
PLM works best on projects that have a well-defined and unchanging design process. When it comes to semiconductor design workflow, change is inevitable. Each new process technology brings a new set of challenges that require adjustments and possibly new tooling.
Total Cost of Ownership
Implementing a PLM tool into an IC design environment takes a great amount of customization and integration. It requires a large amount of code that must be tested and maintained, with any changes in tooling and methodology being extremely disruptive.
Full-time resources are needed for administration of the system, fixing bugs with the custom integrations, and planning and maintaining consistency amid new requirements and changes to the design flow. These factors all contribute to a high cost of maintenance and total cost of ownership.
PLM Systems Are Project-Centric, Not IP-Centric
A traditional PLM model builds a single product from the ground up. In today’s SoCs, the emphasis is on attempting to reuse existing IP from previous projects or from IP vendors. This design environment of IP reuse is a crucial factor in the semiconductor industry to maintain profitability.
The Solution: IP Lifecycle Management
While fulfilling an important need for large scale product development in automotive, aerospace, and other large industries, a traditional PLM model suffers from major barriers to adoption in the semiconductor space. The high TCO and generally inflexible workflow is a bitter pill to swallow in a dynamic design environment, and generally seems unsuited for IC design.
A new type of lifecycle management — IP lifecycle management (IPLM) — is required to enable an IP-centric, transparent approach to managing the IP ecosystem for large SoCs. IPLM is low maintenance with relatively few insertion points into the user workflow and supplements the existing design environment with a powerful workspace management and multisite data management platform that are prerequisites for a SoC design flow.
Reduce Your TCO With IPLM
Learn more about the basic tenets of an IPLM system (IP-centric design flows, hierarchical IP configurations, and more) and how an IPLM tool can reduce the total cost of ownership by embracing the customer workflow.
Why Methodics IPLM?
The Methodics IPLM platform centrally maintains project configurations (akin to a Bill of a Materials in a PLM tool) and user/group and IP permissions. And it can organize requirements and documentation by IP, user workspaces, and hierarchical dependencies. It provides the most critical functions of a PLM system, but without the cost and increased maintenance overhead.
Talk with one of our IP experts today to learn more about how the Methodics IPLM platform can help your organization solve PLM challenges in your semiconductor design environment. Click below to connect with us or schedule a demo.
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