semiconductor design partitioning
October 29, 2021

What Is Design Partitioning?

Design
IP Lifecycle Management

Historically, SoC’s have been designed in a project-centric design style. But with the proliferation of IP-centric architectures and methodologies, thought needs to go into an optimal design partitioning.  

That’s what we break down in this blog. Read along or jump ahead to the section that interests you most:

What Is Design Partitioning?

Design partitioning is the practice of dividing a system on chip (SoC) into small blocks. This allows you to efficiently manage semiconductor designs as a related set of functional blocks.

Semiconductor designs are most efficiently managed as related sets of functional blocks. And Methodics IPLM was developed specifically to enable this workflow.

Design Partitioning With Methodics IPLM

You can achieve significant benefits — accelerated delivery, reduced risks, lower costs — with design partitioning. Learn how Methodics IPLM makes it easy. 
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Best Practices For Design Partitioning

To ensure optimal partitioning, you need to follow the best practices.

1. Give Each IP a Primary Function

Functional blocks are the fundamental units of the design. Each should be represented by its own IP object. This makes it simple to understand the block via the requirements, simulation data, and documentation associated with its IP object.

Functional blocks are often composed of sub-blocks with their own functions. In most cases, these too should be their own IPs and associated hierarchically as children of the higher-level block.

The potential for IP reuse is another key consideration. If a functional block is used in multiple places in one product or between multiple products, it makes sense for it to be its own IP.

2. Release Designs At Will

If a user or group is responsible for a section of the design, then they should be fully in control of making a new release of that section. If the IP spans their block — as well as other blocks — the readiness of the other blocks may interfere with their ability to make a release.

Capturing the state of the design early and often is a key to getting the most out of Methodics IPLM. The release operation is extremely lightweight and each release promotes visibility into the state of the design. Methodics IPLM tracks the relationships between IPs, so much is gained and nothing is lost by making each functional block its own IP.

3. Streamline Design Through Hierarchy

Methodics IPLM’s hierarchical capabilities allow a structured handoff between producers and consumers of IP blocks, so the hierarchy should take this into account:

  • Producers typically want to see the latest versions of the files in an IP.
  • Consumers want to see a fixed version so that the data doesn’t change until they request it.

Producers at one level become consumers of the level below, through as many layers as are required. Producers do their design, run validation, and — once an appropriate level of quality is achieved — automatically alert the next level up that their release is ready to consume.

This hierarchical organization benefits consumers and producers at each level. And it dramatically reduces the overhead of figuring out what the right configuration is.

Partitioning Your Design With Methodics IPLM

Methodics IPLM enables you to achieve optimal design partitioning.

That’s because Methodics IPLM provides the unique benefit of a view of all designs in an organization that is centralized and always up-to-date, while at the same time simultaneously simplifying and streamlining the semiconductor development experience.

Find out how using Methodics IPLM allows you to partition designs so you can accelerate delivery, reduce risks, and lower costs.

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